The present invention relates to a semiconductor integrated circuit device; and, more particularly, the invention relates to a technique which is effective for use in both an output-system circuit of the type which is employed in a semiconductor memory, such as a dynamic RAM (Random Access Memory), wherein an internal circuit is principally activated based on a reduced voltage, and a logic-in level shift circuit employed in the output-system circuit.
In a highly integrated semiconductor memory, a system for activating an internal circuit based on a voltage which has been stepped-down or reduced from an external source voltage has been widely used to ensure reliability of a micro-fabricated device and to reduce the power consumption thereof. Japanese Patent Application Laid-Open No. Hei 9-270191 discloses an example of a dynamic RAM equipped with such a de-boosting circuit.